DCP71150C012010H0 16 位数字信号控制器

VE4003S2B4

The core of this series of devices has 24 bit instruction words. The program counter (PC) is 23 bits wide, and the Least Significant bit (LSb) is always clear (see Section 3.1, “Program Address Space”). Except for certain specialized instructions, the Most Significant bit (MSb) is ignored during normal program execution. In view of this, the PC can address a user program space of up to 4M instruction words. It uses an instruction prefetch mechanism to help maintain throughput. The DO and REPEAT instructions support the loop structure of a program without the overhead of loop count management, which can be interrupted at any time.
The working register array consists of 16 16-bit registers, each of which can act as a data, address, or address offset register. The working register (W15) is used as a software stack pointer for interrupt and invoke operations. The data space is 64 KB (32K words), and it is divided into two pieces, called the X data store and the Y data store. Each storage area has its own Address Generation Unit (AGU). Most instructions operate only through the X storage AGU, so that the data space is separate and unified to the outside world. The multiply-accumulator (MAC) class dual-source operand DSP instruction operates through the AGU of X and Y, dividing the data address space into two parts (see Section 3.2, “Data Address Space”). The boundaries of the X and Y data Spaces are device-specific and cannot be modified by the user. Each data word consists of 2 bytes, and most instructions can address the data by word or byte.
There are two ways to access data in the program memory:
You can optionally map the high 32 KB of data storage Space to the lower half of the Program space (user space) within any 16K program word boundary defined by the 8-bit Program Space VisibilityPage (PSVPAG) register. Program space to data space mapping allows any instruction to access the program space as it would the data space. But access takes an additional instruction cycle. Only the lower 16 bits of each instruction word can be accessed using this method.
• Linear indirect access to 32K word pages in program space can also be achieved using working registers via table read/table write instructions. All 24 bits of an instruction word can be accessed using table read and table write instructions.
Both the X and Y address Spaces support overhead circular buffers (modular addressing). Modular addressing is mainly used to reduce the loop overhead of DSP algorithms.
The X AGU also supports bit-reversed addressing of the target Effective Address (EA), which greatly simplifies the reordering of input or output data by the Base 2 FFT algorithm. For more information on modular and bit-reversed addressing, see Section 4.0, “Address Generator Units.” The kernel supports intrinsic (operand free) addressing, relative addressing, immediate addressing, memory direct addressing, register direct and register indirect addressing, and register offset and immediate offset addressing modes. Each instruction is associated with a predefined set of addressing modes based on its functional requirements. For most instructions, the kernel can perform one data (or program data) memory read, one working register (data) read, one data memory write, and one program (instruction) memory read per instruction cycle. Therefore, instructions with 3 operands can be supported so that C = A+ B operations can be executed in a single cycle.